Real, based and virtual addressing structures have been used in various prior art apparatus. In a real address environment the memory address is sent directly to the memory, with or without address mode modification, and utilized by the memory as an absolute memory address. In a based memory addressing environment a portion of the memory address is utilized to select a base register, the contents of which are then added or concatenated to the remainder of the memory address, again with or without mode modification. An example of a based addressing mechanism is disclosed in U.S. Pat. No. 3,731,283, Lewis R. Carlson, et al, Digital Computer Incorporating Relative Addressing of Instructions. Virtual memory addressing environments, often providing a memory address field larger than the capacity of the resident memory, provide for the actual memory address computation by a translation into a lookup table with a portion of the original address which will provide a pointer to be used as an absolute reference into resident memory from which an index is taken with another portion of the original address, again with or without address mode modification. This virtual translation means may be accomplished through one or more steps. The address utilized by the apparatus in the present invention is a four segment address utilizing three translation steps called page, segment and process with the fourth part of the address being utilized as the index once the absolute memory pointer address is determined. Examples of virtual memory systems in the prior art are illustrated by U.S. Pat. No. 3,614,746, Jacob Fredrik Klinkhamer, Memory Addressing Device Using Arbitrary Directed Graph Structure, and U.S. Pat. No. 3,761,881, David W. Anderson, et al, Address Translation Storage Scheme For Virtual Memory System.
While each of these three memory addressing structures are well known in the prior art and have been well documented, they are relatively inflexible in changing from one of the addressing structures to another. Each of the address structures requires a substantial commitment in hardware to support the address generation mechanism and in the software, the different schemes generally not being software compatible. The solution to the problem of changing from either a real or based address structure to a virtual address structure typically has been to "add-on" the virtual address generation mechanism to the final address previously generated by the old addressing mechanism. This solution results in excessive waste of hardware and a serious deterioration in system operating speed.
Further, in prior art virtual address structures a four segment computer address as is utilized in the present invention, containing process, segment, page and offset identifiers, and hence containing three levels of virtual translation, typically require four memory references. One memory reference is required to obtain the process pointer so that a second memory reference can obtain the segment pointer and still a third memory reference can obtain the page pointer, at which point the absolute memory address of the data word to be retrieved is known. A fourth memory reference then is required to actually obtain the data word.